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parallel nor flash embedded memory m29w256gh, m29w256gl features ? supply voltage C v cc = 2.7C3.6v (program, erase, read) C v ccq = 1.65C3.6v (i/o buffers) C v pph = 12v for fast program (optional) ? asynchronous random/page read C page size: 8 words or 16 bytes C page access: 25ns, 30ns C random access: 60ns 1 , 70ns, 80ns ? fast program commands: 32-word (64-byte) write buffer ? enhanced buffered program commands: 256-word ? program time C 16s per byte/word typ C chip program time: 10s with v pph and 16s with- out v pph ? memory organization C uniform blocks: 256 main blocks, 128kb, or 64- kwords each ? program/erase controller C embedded byte/word program algorithms ? program/erase suspend and resume capability C read from any block during a program sus- pend operation C read or program another block during an erase suspend operation ? unlock bypass, block erase, chip erase, write to buf- fer and program C fast buffered/batch programming C fast block/chip erase ? v pp /wp# pin protection C protects first or last block regardless of block -protection settings ? software protection C volatile protection C nonvolatile protection C password protection ? extended memory block C 128-word (256-byte) memory block for perma- nent, secure identification C programmed or locked at the factory or by the customer ? common flash interface C 64-bit security code ? low power consumption: standby and automatic mode ? jesd47h-compliant C 100,000 minimum program/erase cycles per block C data retention: 20 years (typ) ? 65nm single-level cell (slc) process technology ? fortified bga, tbga, and tsop packages ? "green" packages available C rohs-compliant C halogen-free ? automotive device grade (6) temperature: C40c to +85c (automotive grade-certified) ? automotive device grade (3) temperature: C40c to +125c (automotive grade-certified) note: 1. the 60ns device is available upon customer request. 256mb: 3v embedded parallel nor flash features pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
part numbering information available with extended memory block prelocked by micron. devices are shipped from the factory with memory content bits erased to 1. for available options, such as packages or high/low protection, or for further information, contact your micron sales representative. part numbers can be verified at www.micron.com . feature and specifica- tion comparison by device type is available at www.micron.com/products . contact the factory for devices not found. table 1: part number information part number category category details notes device type m29w operating voltage w = v cc = 2.7 to 3.6v device function 256gh = 256mb (x8/x16) page, uniform block flash memory, highest block protected by v pp /wp# 256gl = 256mb (x8/x16) page, uniform block flash memory, lowest block protected by v pp /wp# speed 70 = 70ns 1 60 = 60ns 1, 2 7a = 70ns 1, 3 package n = 56-pin tsop, 14mm x 20mm, lead-free, halogen-free, rohs-compliant za = 64-ball tbga, 10mm x 13mm, lead-free, halogen-free, rohs-compliant zs = 64-ball fortified bga, 11mm x 13mm temperature range 1 = 0 to 70c 6 = C40c to +85c 3 = C40c to +125c shipping options e = rohs-compliant package, standard packing f = rohs-compliant package, tape and reel packing notes: 1. 80ns if v ccq = 1.65v to v cc . 2. the 60ns device is available upon customer request. 3. automotive-qualified, available only with option 6. qualified and characterized according to aec q100 and q003 or equivalent; advanced screening according to aec q001 and q002 or equivalent. 256mb: 3v embedded parallel nor flash features pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
contents general description ......................................................................................................................................... 7 signal assignments ........................................................................................................................................... 8 signal descriptions ......................................................................................................................................... 10 memory organization .................................................................................................................................... 11 memory configuration ............................................................................................................................... 11 memory map C 256mb density ................................................................................................................... 11 bus operations ............................................................................................................................................... 12 read .......................................................................................................................................................... 12 write .......................................................................................................................................................... 12 standby and automatic standby ................................................................................................................. 12 output disable ........................................................................................................................................... 13 reset .......................................................................................................................................................... 13 registers ........................................................................................................................................................ 14 status register ............................................................................................................................................ 14 lock register .............................................................................................................................................. 19 standard command definitions C address/data cycles ................................................................................... 21 read operations ........................................................................................................................................... 23 read/reset command ............................................................................................................................ 23 read cfi command .................................................................................................................................. 23 auto select operations .............................................................................................................................. 24 auto select command ........................................................................................................................... 24 bypass operations .......................................................................................................................................... 27 unlock bypass command ...................................................................................................................... 27 unlock bypass reset command ............................................................................................................ 27 program operations ....................................................................................................................................... 28 program command ................................................................................................................................ 28 unlock bypass program command ..................................................................................................... 28 write to buffer program command .................................................................................................. 28 unlock bypass write to buffer program command ....................................................................... 31 write to buffer program confirm command .................................................................................. 31 buffered program abort and reset command ................................................................................ 31 program suspend command ................................................................................................................ 31 program resume command .................................................................................................................. 32 enter and exit enhanced buffered program command ................................................................ 32 enhanced buffered program command ........................................................................................... 32 enhanced buffered program abort and reset command ............................................................ 35 erase operations ............................................................................................................................................ 36 chip erase command .............................................................................................................................. 36 unlock bypass chip erase command ................................................................................................... 36 block erase command ........................................................................................................................... 36 unlock bypass block erase command ................................................................................................ 37 erase suspend command ....................................................................................................................... 37 erase resume command ........................................................................................................................ 38 block protection command definitions C address/data cycles ........................................................................ 39 protection operations .................................................................................................................................... 42 lock register commands ...................................................................................................................... 42 password protection commands ....................................................................................................... 42 nonvolatile protection commands .................................................................................................. 42 nonvolatile protection bit lock bit commands ............................................................................ 44 volatile protection commands .......................................................................................................... 44 256mb: 3v embedded parallel nor flash features pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
extended memory block commands .................................................................................................. 44 exit protection command .................................................................................................................... 45 device protection ........................................................................................................................................... 46 hardware protection .................................................................................................................................. 46 software protection .................................................................................................................................... 46 volatile protection mode ............................................................................................................................. 47 nonvolatile protection mode ...................................................................................................................... 47 password protection mode .......................................................................................................................... 48 common flash interface ................................................................................................................................ 49 power-up and reset characteristics ................................................................................................................ 53 absolute ratings and operating conditions ..................................................................................................... 56 dc characteristics .......................................................................................................................................... 58 read ac characteristics .................................................................................................................................. 60 write ac characteristics ................................................................................................................................. 63 accelerated program, data polling/toggle ac characteristics ........................................................................... 70 program/erase characteristics ........................................................................................................................ 72 package dimensions ....................................................................................................................................... 73 revision history ............................................................................................................................................. 76 rev. c C 7/13 ............................................................................................................................................... 76 rev. b C 5/13 ............................................................................................................................................... 76 rev. a C 5/12 ............................................................................................................................................... 76 256mb: 3v embedded parallel nor flash features pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
list of figures figure 1: logic diagram ................................................................................................................................... 7 figure 2: 56-pin tsop (top view) .................................................................................................................... 8 figure 3: 64-ball fortified bga and 64-ball tbga ............................................................................................. 9 figure 4: data polling flowchart .................................................................................................................... 16 figure 5: toggle bit flowchart ........................................................................................................................ 17 figure 6: status register polling flowchart ..................................................................................................... 18 figure 7: lock register program flowchart ..................................................................................................... 20 figure 8: write to buffer program flowchart ........................................................................................ 30 figure 9: enhanced buffered program flowchart ................................................................................ 34 figure 10: program/erase nonvolatile protection bit algorithm ...................................................................... 43 figure 11: software protection scheme .......................................................................................................... 48 figure 12: power-up timing .......................................................................................................................... 53 figure 13: reset ac timing C no program/erase operation in progress ...................................................... 54 figure 14: reset ac timing during program/erase operation .................................................................... 55 figure 15: ac measurement load circuit ....................................................................................................... 57 figure 16: ac measurement i/o waveform ..................................................................................................... 57 figure 17: random read ac timing (8-bit mode) ........................................................................................... 61 figure 18: random read ac timing (16-bit mode) ......................................................................................... 61 figure 19: page read ac timing (16-bit mode) ............................................................................................... 62 figure 20: we#-controlled program ac timing (8-bit mode) .......................................................................... 64 figure 21: we#-controlled program ac timing (16-bit mode) ......................................................................... 65 figure 22: ce#-controlled program ac timing (8-bit mode) ........................................................................... 67 figure 23: ce#-controlled program ac timing (16-bit mode) ......................................................................... 68 figure 24: chip/block erase ac timing (8-bit mode) ...................................................................................... 69 figure 25: accelerated program ac timing ..................................................................................................... 70 figure 26: data polling ac timing .................................................................................................................. 71 figure 27: toggle/alternative toggle bit polling ac timing (8-bit mode) .......................................................... 71 figure 28: 56-pin tsop C 14mm x 20mm ........................................................................................................ 73 figure 29: 64-ball tbga C 10mm x 13mm ....................................................................................................... 74 figure 30: 64-ball fortified bga C 11mm x 13mm ........................................................................................... 75 256mb: 3v embedded parallel nor flash features pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
list of tables table 1: part number information ................................................................................................................... 2 table 2: signal descriptions ........................................................................................................................... 10 table 3: 256mb, blocks[255:0] ........................................................................................................................ 11 table 4: bus operations ................................................................................................................................. 12 table 5: status register bit definitions ........................................................................................................... 14 table 6: operations and corresponding bit settings ........................................................................................ 15 table 7: lock register bit definitions ............................................................................................................. 19 table 8: block protection status ..................................................................................................................... 19 table 9: standard command definitions C address/data cycles, 8-bit and 16-bit ............................................ 21 table 10: read electronic signature ............................................................................................................... 24 table 11: block protection ............................................................................................................................. 26 table 12: block protection command definitions C address/data cycles, 8-bit and 16-bit ............................... 39 table 13: extended memory block address and data ...................................................................................... 44 table 14: v pp /wp# functions ......................................................................................................................... 46 table 15: query structure overview ............................................................................................................... 49 table 16: cfi query identification string ........................................................................................................ 49 table 17: cfi query system interface information .......................................................................................... 50 table 18: device geometry definition ............................................................................................................ 50 table 19: primary algorithm-specific extended query table ........................................................................... 51 table 20: security code area .......................................................................................................................... 52 table 21: power-up wait timing specifications .............................................................................................. 53 table 22: reset ac specifications ................................................................................................................... 54 table 23: absolute maximum/minimum ratings ............................................................................................ 56 table 24: operating conditions ...................................................................................................................... 56 table 25: i/o capacitance 1 ............................................................................................................................ 57 table 26: dc current characteristics .............................................................................................................. 58 table 27: dc voltage characteristics .............................................................................................................. 59 table 28: read ac characteristics .................................................................................................................. 60 table 29: we#-controlled write ac characteristics ......................................................................................... 63 table 30: ce#-controlled write ac characteristics ......................................................................................... 66 table 31: accelerated program and data polling/data toggle ac characteristics .............................................. 70 table 32: program/erase characteristics ........................................................................................................ 72 256mb: 3v embedded parallel nor flash features pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
general description the m29w is an asynchronous, uniform block, parallel nor flash memory device man- ufactured on 65nm single-level cell (slc) technology. read, erase, and program op- erations are performed using a single low-voltage supply. upon power-up, the device defaults to read array mode. the main memory array is divided into uniform blocks that can be erased independent- ly so that valid data can be preserved while old data is purged. program and erase commands are written to the command interface of the memory. an on-chip program/ erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. the end of a program or erase operation can be detected, and any error condition can be identi- fied. the command set required to control the device is consistent with jedec stand- ards. ce#, oe#, and we# control the bus operation of the device and enable a simple con- nection to most microprocessors, often without additional logic. the m29w supports asynchronous random read and page read from all blocks of the array. it features a write to buffer program capability that improves throughput by pro- gramming a buffer of 32 words in one command sequence. also, in x16 mode, the en- hanced buffered program capability improves throughput by programming 256 words in one command sequence. the device v pp /wp# signal enables faster programming. the device contains a 128-word (x16) and 256-byte (x8) extended memory block. the user can program this additional space and then protect it to permanently secure the contents. the device also features different levels of hardware and software protection to secure blocks from unwanted modification. figure 1: logic diagram v cc v ccq a[23:0] we# v pp /wp# dq[14:0] dq15/a-1 v ss 15 ce# oe# rst# byte# ry/by# 256mb: 3v embedded parallel nor flash general description pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
signal assignments figure 2: 56-pin tsop (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 a23 a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# rst# a21 v pp /wp# ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 rfu rfu rfu rfu a16 byte# v ss dq15/a-1 dq7 dq14 dq6 dq13 dq5 dq12 dq4 v cc dq11 dq3 dq10 dq2 dq9 dq1 dq8 dq0 oe# vss ce# a0 rfu v ccq notes: 1. a23 = a[max]. 2. a-1 is the least significant address bit in x8 mode. 256mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 3: 64-ball fortified bga and 64-ball tbga a b c d e f g h a b c d e f g h 1 rfu rfu rfu rfu rfu v ccq rfu rfu 1 rfu rfu rfu rfu rfu v ccq rfu rfu 2 a3 a4 a2 a1 a0 ce# oe# v ss 2 a3 a4 a2 a1 a0 ce# oe# v ss 3 a7 a17 a6 a5 d0 d8 d9 d1 3 a7 a17 a6 a5 d0 d8 d9 d1 4 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 4 ry/by# v pp /wp# a18 a20 d2 d10 d11 d3 5 we# rst# a21 a19 d5 d12 v cc d4 5 we# rst# a21 a19 d5 d12 v cc d4 6 a9 a8 a10 a11 d7 d14 d13 d6 6 a9 a8 a10 a11 d7 d14 d13 d6 7 a13 a12 a14 a15 a16 byte# d15/a-1 v ss 7 a13 a12 a14 a15 a16 byte# d15/a-1 v ss 8 rfu a22 a23 v ccq v ss rfu rfu rfu 8 rfu a22 a23 v ccq v ss rfu rfu rfu top view C ball side down bottom view C ball side up notes: 1. a[23] = a[max]. 2. a-1 is the least significant address bit in x8 mode. 256mb: 3v embedded parallel nor flash signal assignments pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
signal descriptions the signal description table below is a comprehensive list of signals for this device fami- ly. all signals listed may not be supported on this device. see signal assignments for in- formation specific to this device. table 2: signal descriptions name type description a[max:0] input address: selects the cells in the array to access during read operations. during write oper- ations, they control the commands sent to the command interface of the program/erase con- troller. ce# input chip enable: activates the device, enabling read and write operations to be performed. when ce# is high, the device goes to standby, and data outputs are at high-z. oe# input output enable: controls the bus read operation. we# input write enable: controls the bus write operation of the command interface. v pp /wp# input v pp /write protect: provides write protect function and v pph function. these functions protect the lowest or highest block and enable the device to enter unlock bypass mode, re- spectively. (refer to hardware protection and bypass operations for details.) byte# input byte/word organization select: switches between x8 and x16 bus modes. when byte# is low, the device is in x8 mode; when high, the device is in x16 mode. rst# input reset: applies a hardware reset to the device, which is achieved by holding rst# low for at least t plpx. after rst# goes high, the device is ready for read and write operations (after t phel or t rhel, whichever occurs last). (see reset ac specifications for more details.) dq[7:0] i/o data i/o: outputs the data stored at the selected address during a read operation. during write operations, they represent the commands sent to the command interface of the inter- nal state machine. dq[14:8] i/o data i/o: outputs the data stored at the selected address during a read operation when byte# is high. when byte# is low, these pins are not used and are high-z. during write operations, these bits are not used. when reading the status register, these bits should be ig- nored. dq15/a-1 i/o data i/o or address input: when the device operates in x16 bus mode, this pin behaves as data i/o, together with dq[14:8]. when the device operates in x8 bus mode, this pin behaves as the least significant bit of the address. except where stated explicitly otherwise, dq15 = data i/o (x16 mode); a-1 = address input (x8 mode). ry/by# output ready/busy: open-drain output that can be used to identify when the device is performing a program or erase operation. during program or erase operations, ry/by# is low, and is high-z during read mode, auto select mode, and erase suspend mode. after a hard- ware reset, read and write operations cannot begin until ry/by# goes high-z. (see reset ac specifications for more details.) the use of an open-drain output enables the ry/by# pins from several devices to be connec- ted to a single pull-up resistor to v ccq . a low value will then indicate that one (or more) of the devices is (are) busy. a 10,000 or higher resistor is recommended as pull-up resistor to achieve 0.1v v ol . 256mb: 3v embedded parallel nor flash signal descriptions pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 2: signal descriptions (continued) name type description v cc supply supply voltage: provides the power supply for read, program, and erase operations. the command interface is disabled when v cc v lko . this prevents write operations from ac- cidentally damaging the data during power-up, power-down, and power surges. if the pro- gram/erase controller is programming or erasing during this time, then the operation aborts, and the contents being altered will be invalid. a 0.1 f capacitor should be connected between v cc and v ss to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during program and erase operations. (see dc characteristics.) v ccq supply i/o supply voltage: provides the power supply to the i/o pins and enables all outputs to be powered independently from v cc . v ss supply ground: all v ss pins must be connected to the system ground. rfu C reserved for future use: rfus should be not connected. memory organization memory configuration the main memory array is divided into 128kb or 64kw uniform blocks. memory map C 256mb density table 3: 256mb, blocks[255:0] block block size address range (x8) block size address range (x16) start end start end 255 128kb 1fe 0000h 1ff ffffh 64kw 0ff 0000h 0ff ffffh ? ? ? ? ? 127 0fe 0000h 0ff ffffh 07f 0000h 07f ffffh ? ? ? ? ? 63 07e 0000h 07f ffffh 03f 0000h 03f ffffh ? ? ? ? ? 0 000 0000h 001 ffffh 000 0000h 000 ffffh 256mb: 3v embedded parallel nor flash memory organization pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
bus operations table 4: bus operations notes 1 and 2 apply to entire table operation ce# oe# we# rst# v pp /wp# 8-bit mode 16-bit mode a[max:0], dq15/a-1 dq[14:8] dq[7:0] a[max:0] dq15/a-1, dq[14:0] read l l h h x cell address high-z data output cell address data output write l h l h x 3 command address high-z data input 4 command address data input 4 standby h x x h x x high-z high-z x high-z output disable l h h h x x high-z high-z x high-z reset x x x l x x high-z high-z x high-z notes: 1. typical glitches of less than 5ns on ce#, we#, and rst# are ignored by the device and do not affect bus operations. 2. h = logic level high (v ih ); l = logic level low (v il ); x = high or low. 3. if wp# is low, then the highest or the lowest block remains protected, depending on line item. 4. data input is required when issuing a command sequence or when performing data polling or block protection. read bus read operations read from the memory cells, registers, or cfi space. to accelerate the read operation, the memory array can be read in page mode where data is inter- nally read and stored in a page buffer. the page size is 8 words (16 bytes) and is addressed by address inputs a[2:0] in x16 bus mode and a[2:0] plus dq15/a-1 in x8 bus mode. the extended memory blocks and cfi area do not support page read mode. a valid read operation requires setting the appropriate address on the address inputs, taking ce# and oe# low, and holding we# high. data i/o signals output the value. write bus write operations write to the command interface. a valid write operation re- quires setting the appropriate address on the address inputs. these are latched by the command interface on the falling edge of ce# or we#, whichever occurs last. values on data i/o signals are latched by the command interface on the rising edge of ce# or we#, whichever occurs first. oe# must remain high during the entire operation. standby and automatic standby when the device is in read mode, driving ce# high places the device in standby mode and drives data i/os to high-z. supply current is reduced to standby (i cc2 ) by holding ce# within v cc 0.3v. during program or erase operations, the device continues to use the program/erase supply current (i cc3 ) until the operation completes. 256mb: 3v embedded parallel nor flash bus operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
automatic standby enables low power consumption during read mode. when cmos levels (v cc 0.3 v) drive the bus, and following a read operation and a period of inac- tivity specified in dc characteristics, the memory enters automatic standby as internal supply current is reduced to i cc2 . data i/o signals still output data if a read operation is in progress. depending on load circuits connected with data bus, v ccq can have a null consumption when the memory enters automatic standby. output disable data i/os are high-z when oe# is high. reset during reset mode, the device is deselected, and outputs are high-z. the device is in reset mode when rst# is low. power consumption is reduced to standby level inde- pendently from ce#, oe#, or we# inputs. 256mb: 3v embedded parallel nor flash bus operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
registers status register table 5: status register bit definitions note 1 applies to entire table bit name settings description notes dq7 data polling bit 0 or 1, depending on operations monitors whether the program/erase controller has successful- ly completed its operation, or has responded to an erase sus- pend operation. 2, 3, 4 dq6 toggle bit toggles: 0 to 1; 1 to 0; and so on monitors whether the program/erase controller has successful- ly completed its operations, or has responded to an erase suspend operation. during a program/erase operation, dq6 toggles from 0 to 1, 1 to 0, and so on, with each succes- sive read operation from any address. 3, 4, 5 dq5 error bit 0 = success 1 = failure identifies errors detected by the program/erase controller. dq5 is set to 1 when a program, block erase, or chip erase op- eration fails to write the correct data to the memory. 4, 6 dq3 erase timer bit 0 = erase not in progress 1 = erase in progress identifies the start of program/erase controller operation dur- ing a block erase command. before the program/erase con- troller starts, this bit set to 0, and additional blocks to be erased can be written to the command interface. 4 dq2 alternative toggle bit toggles: 0 to 1; 1 to 0; and so on monitors the program/erase controller during erase opera- tions. during chip erase, block erase, and erase suspend operations, dq2 toggles from 0 to 1, 1 to 0, and so on, with each successive read operation from addresses within the blocks being erased. 3, 4 dq1 buffered program abort bit 1 = abort indicates a buffer program operation abort. the buffered program abort and reset command must be issued to re- turn the device to read mode (see write to buffer pro- gram command). notes: 1. the status register can be read during program, erase, or erase suspend operations; the read operation outputs data on dq[7:0]. 2. for a program operation in progress, dq7 outputs the complement of the bit being programmed. for a read operation from the address previously programmed success- fully, dq7 outputs existing dq7 data. for a read operation from addresses with blocks to be erased while an erase suspend operation is in progress, dq7 outputs 0; upon successful completion of the erase suspend operation, dq7 outputs 1. for an erase operation in progress, dq7 outputs 0; upon either operation's successful completion, dq7 outputs 1. 3. after successful completion of a program or erase operation, the device returns to read mode. 4. during erase suspend mode, read operations to addresses within blocks not being erased output memory array data as if in read mode. a protected block is treated the same as a block not being erased. see the toggle flowchart for more information. 5. during erase suspend mode, dq6 toggles when addressing a cell within a block being erased. the toggling stops when the program/erase controller has suspended the erase operation. see the toggle flowchart for more information. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
6. when dq5 is set to 1, a read/reset command must be issued before any subsequent command. table 6: operations and corresponding bit settings note 1 applies to entire table operation address dq7 dq6 dq5 dq3 dq2 dq1 ry/by# notes program any address dq7# toggle 0 C no toggle 0 0 2 program during erase suspend any address dq7# toggle 0 C C C 0 enhanced buffered program any address C toggle 0 C C C 0 buffered program abort any address dq7# toggle 0 C C 1 0 2 program error any address dq7# toggle 1 C C C high-z chip erase any address 0 toggle 0 1 toggle C 0 block erase before time-out erasing block 0 toggle 0 0 toggle C 0 non-erasing block 0 toggle 0 0 no toggle C 0 block erase erasing block 0 toggle 0 1 toggle C 0 non-erasing block 0 toggle 0 1 no toggle C 0 erase suspend erasing block 1 no toggle 0 C toggle C high-z non-erasing block outputs memory array data as if in read mode C high-z block erase error good block address 0 toggle 1 1 no toggle C high-z faulty block address 0 toggle 1 1 toggle C high-z notes: 1. unspecified data bits should be ignored. 2. dq7# for buffer program is related to the last address location loaded. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 4: data polling flowchart start dq7 = data dq5 = 1 dq1 = 1 dq7 = data no no no no yes yes yes yes read dq7, dq5, and dq1 at valid address 1 read dq7 at valid address success failure 2 notes: 1. valid address is the address being programmed or an address within the block being erased. 2. failure results: dq5 = 1 indicates an operation error; dq1 = 1 indicates a write to buf- fer program abort operation. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 5: toggle bit flowchart dq6 = toggle dq5 = 1 dq6 = toggle no no yes yes yes start read dq6 at valid address read dq6, dq5, and dq1 at valid address read dq6 (twice) at valid address success failure 1 dq1 = 1 no yes no note: 1. failure results: dq5 = 1 indicates an operation error; dq1 = 1 indicates a write to buf- fer program abort operation. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 6: status register polling flowchart write to buffer program start dq7 = valid data dq5 = 1 yes no no yes yes dq6 = toggling yes no no no yes program operation no no dq6 = toggling no dq2 = toggling yes yes yes dq1 = 1 read 3 correct data? no yes read 1 read 2 read 2 read 3 device busy: repolling device busy: repolling read 3 program operation complete program operation failure write to buffer program abort timeout failure erase operation complete erase/suspend mode device error read2.dq6 = read3.dq6 read2.dq2 = read3.dq2 read1.dq6 = read2.dq6 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
lock register table 7: lock register bit definitions note 1 applies to entire table bit name settings description notes dq2 password protection mode lock bit 0 = password protection mode enabled 1 = password protection mode disabled (default) places the device permanently in password protection mode. 2 dq1 nonvolatile protection mode lock bit 0 = nonvolatile protection mode enabled with pass- word protection mode permanently disabled 1 = nonvolatile protection mode enabled (default) places the device in nonvolatile protection mode with pass- word protection mode permanently disabled. when shipped from the factory, the device will operate in nonvolatile protec- tion mode, and the memory blocks are unprotected. 2 dq0 extended memory block protection bit 0 = protected 1 = unprotected (default) if the device is shipped with the extended memory block un- locked, the block can be protected by setting this bit to 0. the extended memory block protection status can be read in auto select mode by issuing an auto select command. notes: 1. the lock register is a 16-bit, one-time programmable register. dq[15:3] are reserved and are set to a default value of 1. 2. the password protection mode lock bit and nonvolatile protection mode lock bit cannot both be programmed to 0. any attempt to program one while the other is programmed causes the operation to abort, and the device returns to read mode. the device is ship- ped from the factory with the default setting. table 8: block protection status nonvolatile protection bit lock bit 1 nonvolatile protection bit 2 volatile protection bit 3 block protection status block protection status 1 1 1 00h block unprotected; nonvolatile protection bit changeable. 1 1 0 01h block protected by volatile protection bit; nonvolatile protec- tion bit changeable. 1 0 1 01h block protected by nonvolatile protection bit; nonvolatile protection bit changeable. 1 0 0 01h block protected by nonvolatile protection bit and volatile protection bit; nonvolatile protection bit changeable. 0 1 1 00h block unprotected; nonvolatile protection bit unchangeable. 0 1 0 01h block protected by volatile protection bit; nonvolatile protec- tion bit unchangeable. 0 0 1 01h block protected by nonvolatile protection bit; nonvolatile protection bit unchangeable. 0 0 0 01h block protected by nonvolatile protection bit and volatile protection bit; nonvolatile protection bit unchangeable. notes: 1. nonvolatile protection bit lock bit: when cleared to 1, all nonvolatile protection bits are unlocked; when set to 0, all nonvolatile protection bits are locked. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
2. block nonvolatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. 3. block volatile protection bit: when cleared to 1, the block is unprotected; when set to 0, the block is protected. figure 7: lock register program flowchart start done? dq5 = 1 no no yes yes enter lock register command set address/data (unlock) cycle 1 address/data (unlock) cycle 2 address/data cycle 3 program lock register address/data cycle 1 address/data cycle 2 polling algorithm success: exit protection command set (returns to device read mode) address/data cycle 1 address/data cycle 2 failure: read/reset (returns device to read mode) notes: 1. each lock register bit can be programmed only once. 2. see the block protection command definitions table for address/data cycle details. 256mb: 3v embedded parallel nor flash registers pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 20 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
standard command definitions C address/data cycles table 9: standard command definitions C address/data cycles, 8-bit and 16-bit note 1 applies to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th 5th 6th a d a d a d a d a d a d read and auto select operations read/reset (f0h) x8 x f0 aaa aa 555 55 x f0 x16 x f0 555 aa 2aa 55 x f0 read cfi (98h) x8 aa 98 x16 55 auto select (90h) x8 aaa aa 555 55 aaa 90 note 2 note 2 2, 3, 4 x16 555 2aa 555 bypass operations unlock bypass (20h) x8 aaa aa 555 55 aaa 20 x16 555 2aa 555 unlock bypass reset (90h/00h) x8 x 90 x 00 x16 program operations program (a0h) x8 aaa aa 555 55 aaa a0 pa pd x16 555 2aa 555 unlock bypass program (a0h) x8 x a0 pa pd 5 x16 write to buffer program (25h) x8 aaa aa 555 55 bad 25 bad n pa pd 6, 7, 8 x16 555 2aa unlock bypass write to buffer program (25h) x8 bad 25 bad n pa pd 5 x16 write to buffer program confirm (29h) x8 bad 29 x16 buffered program abort and reset (f0h) x8 aaa aa 555 55 aaa f0 x16 555 2aa 555 enter enhanced buffered program (38h) x8 na x16 555 aa 2aa 55 555 38 enhanced buffered program (33h) x8 na 9 x16 bad 33 bad (00) data bad (01) data 256mb: 3v embedded parallel nor flash standard command definitions C address/data cycles pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 21 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 9: standard command definitions C address/data cycles, 8-bit and 16-bit (continued) note 1 applies to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th 5th 6th a d a d a d a d a d a d exit enhanced buffered program (90h) x8 na x16 x 90 x 00 enhanced buffered program abort (f0h) x8 na x16 555 aa 2aa 55 555 f0 program suspend (b0h) x8 x b0 x16 program resume (30h) x8 x 30 x16 erase operations chip erase (80/10h) x8 aaa aa 555 55 aaa 80 aaa aa 555 55 aaa 10 x16 555 2aa 555 555 2aa 555 unlock bypass chip erase (80/10h) x8 x 80 x 10 5 x16 block erase (80/30h) x8 aaa aa 555 55 aaa 80 aaa aa 555 55 bad 30 10 x16 555 2aa 555 555 2aa unlock bypass block erase (80/30h) x8 x 80 bad 30 5 x16 erase suspend (b0h) x8 x b0 x16 erase resume (30h) x8 x 30 x16 notes: 1. a = address; d = data; x = "don't care"; bad = any address in the block; n = number of bytes to be programmed; pa = program address; pd = program data; gray shading = not applicable. all values in the table are hexadecimal. some commands require both a com- mand code and subcode. 2. these cells represent read cycles (versus write cycles for the others). 3. auto select enables the device to read the manufacturer code, device code, block pro- tection status, and extended memory block protection indicator. 4. auto select addresses and data are specified in the electronic signature table and the extended memory block protection table. 5. for any unlock bypass erase/program command, the first two unlock cycles are unnecessary. 6. bad must be the same as the address loaded during the write to buffer program third and fourth cycles. 7. write to buffer program operation: maximum cycles = 68 (x8) and 36 (x16). un- lock bypass write to buffer program operation: maximum cycles = 66 (x8) and 34 (x16). write to buffer program operation: n + 1 = bytes to be programmed; maxi- mum buffer size = 64 bytes (x8) and 32 words (x16). 256mb: 3v embedded parallel nor flash standard command definitions C address/data cycles pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 22 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
8. for x8, a[max:5] address pins should remain unchanged while a[4:0] and a-1 pins are used to select a byte within the n + 1 byte page. for x16, a[max:5] address pins should remain unchanged while a[4:0] pins are used to select a word within the n + 1 word page. 9. the following is content for address/data cycles 256 through 258: bad (fe) - data; bad (ff) - data; bad (00) - 29. 10. block erase address cycles can extend beyond six address/data cycles, depending on the number of blocks to erase. read operations read/reset command the read/reset (f0h) command returns the device to read mode and resets the errors in the status register. one or three bus write operations can be used to issue the read/reset command. to return the device to read mode, this command can be issued between bus write cycles before the start of a program or erase operation. if the read/reset com- mand is issued during the timeout of a block erase operation, the device requires up to 10 s to abort, during which time no valid data can be read. read cfi command the read cfi (98h) command puts the device in read cfi mode and is valid only when the device is in read array or auto select mode. one bus write cycle is required to issue the command. once in read cfi mode, bus read operations will output data from the cfi memory area. a read/reset command must be issued to return the device to the previous mode (read array or auto select ). a second read/reset command is required to put the device in read array mode from auto select mode. 256mb: 3v embedded parallel nor flash read operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 23 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
auto select operations auto select command at power-up or after a hardware reset, the device is in read mode. it can then be put in auto select mode by issuing an auto select (90h) command or by applying v id to a9. auto select mode enables the following device information to be read: ? electronic signature, which includes manufacturer and device code information, as shown in the electronic signature table. ? block protection, which includes the block protection status and extended memory block protection indicator, as shown in the block protection table. electronic signature or block protection information is read by executing a read opera- tion with control signals and addresses set, as shown in the read electronic signature table or the block protection table, respectively. auto select mode can be used by the programming equipment to automatically match a device with the application code to be programmed. three consecutive bus write operations are required to issue an auto select com- mand. the device remains in auto select mode until a read/reset or read cfi com- mand is issued. the device cannot enter auto select mode when a program or erase operation is in progress (ry/by# low). however, auto select mode can be entered if the program or erase operation has been suspended by issuing a program suspend or erase sus- pend command. to enter auto select mode by appling v id to a9, see the read electronic signature table and the block protection table. auto select mode is exited by performing a reset. the device returns to read mode un- less it entered auto select mode after an erase suspend or program suspend command, in which case it returns to erase or program suspend mode. table 10: read electronic signature note 1 applies to entire table signal read cycle notes manufacturer code device code 1 device code 3 device code 3 ce# l l l l oe# l l l l we# h h h h address input, 8-bit and 16-bit a[max:10] x x x x a9 v id v id v id v id 2 a8 x x x x a[7:5] l l l l a4 x x x x a[3:1] l l h h 256mb: 3v embedded parallel nor flash auto select operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 24 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 10: read electronic signature (continued) note 1 applies to entire table signal read cycle notes manufacturer code device code 1 device code 3 device code 3 a0 l h l h address input, 8-bit only dq[15]/a-1 x x x x data i/o, 8-bit only dq[14:8] x x x x dq[7:0] 20h 7eh 21h xx data i/o, 16-bit only dq[15]/a-1, and dq[14:0] 0020h 227eh 2221h xxxx notes: 1. h = logic level high (v ih ); l = logic level low (v il ); x = high or low. 2. when using the auto select command to enter auto select mode, applying v id to a9 is not required. a9 can be either v il or v ih . 3. xx = 01h for m29w128gh and 00h for m29w128gl. 4. xxxx = 2201h for m29w128gh and 2200h for m29w128gl. 256mb: 3v embedded parallel nor flash auto select operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 25 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 11: block protection note 1 applies to entire table signal read cycle notes extended memory block verify indicator (gl) extended memory block verify indicator (gh) block protection status indicator ce# l l l oe# l l l we# h h h address input, 8-bit and 16-bit a[max:16] x x block base address a[15:10] x x x a9 v id v id v id 2 a8 x x x a[7:5] l l l a4 x x x a[3:2] l l l a1 h h h a0 h h l address input, 8-bit only dq[15]/a-1 x x x data i/o, 8-bit only dq[14:8] x x x dq[7:0] 89h 99h 01h 3, 5 09h 19h 00h 4, 6 data i/o, 16-bit only dq[15]/a-1, and dq[14:0] 0089h 0099h 0001h 3, 5 0009h 0019h 0000h 4, 6 notes: 1. read cycle output to dq7 = extended memory block protection indicator; gl = high block protection; gh = low block protection; bps = block protection status; h = logic level high (v ih ); l = logic level low (v il ); x = high or low. 2. when using the auto select command to enter auto select mode, applying v id to a9 is not required. a9 can be either v il or v ih . 3. extended memory blocks are micron-prelocked (permanent). 4. extended memory blocks are customer-lockable. 5. block protection status = protected: 01h (in x8 mode) is output on dq[7:0]. 6. block protection status = unprotected: 00h (in x8 mode) is output on dq[7:0]. 256mb: 3v embedded parallel nor flash auto select operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 26 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
bypass operations unlock bypass command the unlock bypass (20h) command is used to place the device in unlock bypass mode. three bus write operations are required to issue the unlock bypass com- mand. when the device enters unlock bypass mode, the two initial unlock cycles required for a standard program or erase operation are not needed, thus enabling faster total program or erase time. the unlock bypass command is used in conjunction with unlock bypass pro- gram or unlock bypass erase commands to program or erase the device faster than with standard program or erase commands. using these commands can save considerable time when the cycle time to the device is long. when in unlock bypass mode, only the following commands are valid: ? the unlock bypass program command can be issued to program addresses within the device. ? the unlock bypass block erase command can then be issued to erase one or more memory blocks. ? the unlock bypass chip erase command can be issued to erase the whole mem- ory array. ? the unlock bypass write to buffer program and unlock bypass en- hanced write to buffer program commands can be issued to speed up the programming operation. ? the unlock bypass reset command can be issued to return the device to read mode. in unlock bypass mode, the device can be read as if in read mode. in addition to the unlock bypass command, when v pp /wp# is raised to v pph , the de- vice automatically enters unlock bypass mode. when v pp /wp# returns to v ih or v il , the device is no longer in unlock bypass mode, and normal operation resumes. the transi- tions from v ih to v pph and from v pph to v ih must be slower than t vhvpp. (see the accel- erated program, data polling/toggle ac characteristics.) note: micron recommends entering and exiting unlock bypass mode using the enter unlock bypass and unlock bypass reset commands rather than raising v pp /wp# to v pph . v pp /wp# should never be raised to v pph from any mode except read mode; oth- erwise, the device may be left in an indeterminate state. v pp /wp# should not remain at v pph for than 80 hours cumulative. unlock bypass reset command the unlock bypass reset (90/00h) command is used to return to read/reset mode from unlock bypass mode. two bus write operations are required to issue the un- lock bypass reset command. the read/reset command does not exit from un- lock bypass mode. 256mb: 3v embedded parallel nor flash bypass operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 27 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
program operations program command the program (a0h) command can be used to program a value to one address in the memory array. the command requires four bus write operations; the final write op- eration latches the address and data in the internal state machine and starts the pro- gram/erase controller. after programming has started, bus read operations output the status register content. programming can be suspended and then resumed by issuing a program suspend command and a program resume command, respectively. if the address falls in a protected block, the program command is ignored, and the data remains unchanged. the status register is not read, and no error condition is given. after the program operation has completed, the device returns to read mode, unless an error has occurred. when an error occurs, bus read operations to the device contin- ue to output the status register. a read/reset command must be issued to reset the error condition and return the device to read mode. the program command cannot change a bit set to 0 back to 1, and an attempt to do so is masked during a program operation. instead, an erase command must be used to set all bits in one memory block or in the entire memory from 0 to 1. the program operation is aborted by performing a reset or by powering-down the de- vice. in this case, data integrity cannot be ensured, and the words or bytes that were aborted should be reprogrammed. unlock bypass program command when the device is in unlock bypass mode, the unlock bypass program (a0h) command can be used to program one address in the memory array. the command re- quires two bus write operations instead of four required by a standard program command; the final write operation latches the address and data and starts the pro- gram/erase controller. (the standard program command requires four bus write operations.) the program operation using the unlock bypass program com- mand behaves identically to the program operation using the program command. the operation cannot be aborted. a bus read operation to the memory outputs the status register. write to buffer program command the write to buffer program (25h) command makes use of the 32-word program buffer to speed up programming. a maximum of 32 words can be loaded into the pro- gram buffer. the write to buffer program command dramatically reduces system programming time compared to the standard non-buffered program command. when issuing a write to buffer program command, v pp /wp# can be either held high or raised to v pph . also, it can be held low if the block is not the lowest or highest block, depending on the part number. the following successive steps are required to is- sue the write to buffer program command: first, two unlock cycles are issued. next, a third bus write cycle sets up the write to buffer program command. the set-up code can be addressed to any location 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 28 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
within the targeted block. then, a fourth bus write cycle sets up the number of words/ bytes to be programmed. value n is written to the same block address, where n + 1 is the number of words/bytes to be programmed. value n + 1 must not exceed the size of the program buffer, or the operation will abort. a fifth cycle loads the first address and data to be programmed. last, n bus write cycles load the address and data for each word/ byte into the program buffer. addresses must lie within the range from the start address +1 to the start address + (n - 1) . optimum programming performance and lower power usage are achieved by aligning the starting address at the beginning of a 32-word boundary. any buffer size smaller than 32 words is allowed within a 32-word boundary, while all addresses used in the op- eration must lie within the 32-word boundary. in addition, any crossing boundary buf- fer program will result in a program abort. to program the content of the program buffer, this command must be followed by a write to buffer program confirm command. if an address is written several times during a write to buffer program operation, the address/data counter will be decremented at each data load operation, and the data will be programmed to the last word loaded into the buffer. invalid address combinations or the incorrect sequence of bus write cycles will abort the write to buffer program command. the status register bits dq1, dq5, dq6, dq7 can be used to monitor the device status during a write to buffer program operation. the write buffer program command should not be used to change a bit set to 0 back to 1, and an attempt to do so is masked during the operation. rather than the write buffer program command, the erase command should be used to set memory bits from 0 to 1. 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 29 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 8: write to buffer program flowchart abort write to buffer write buffer data, start address start x = n write n, 1 block address write to buffer and program aborted 2 write to a different block address x = 0 write next data, 3 program address pair write to buffer confirm, block address x = x - 1 yes no yes no dq7 = data no yes dq5 = 1 yes no dq1 = 1 no yes write to buffer command, block address read status register (dq1, dq5, dq7) at last loaded address dq7 = data 4 no yes check status register (dq5, dq7) at last loaded address fail or abort 5 end first three cycles of the write to buffer program command notes: 1. n + 1 is the number of addresses to be programmed. 2. the buffered program abort and reset command must be issued to return the de- vice to read mode. 3. when the block address is specified, any address in the selected block address space is acceptable. however, when loading program buffer address with data, all addresses must fall within the selected program buffer page. 4. dq7 must be checked because dq5 and dq7 may change simultaneously. 5. if this flowchart location is reached because dq5 = 1, then the write to buffer pro- gram command failed. if this flowchart location is reached because dq1 = 1, then the write to buffer program command aborted. in both cases, the appropriate reset command must be issued to return the device to read mode: a reset command if the operation failed; a write to buffer program abort and reset command if the op- eration aborted. 6. see the standard command definitions C address/data cycles, 8-bit and 16-bit table for details about the write to buffer program command sequence. 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 30 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
unlock bypass write to buffer program command when the device is in unlock bypass mode, the unlock bypass write to buffer (25h) command can be used to program the device in fast program mode. the com- mand requires two bus write operations fewer than the standard write to buffer program command. the unlock bypass write to buffer program command behaves the same way as the write to buffer program command: the operation cannot be aborted, and a bus read operation to the memory outputs the status register. the write to buffer program confirm command is used to confirm an un- lock bypass write to buffer program command and to program the n + 1 words/bytes loaded in the program buffer by this command. write to buffer program confirm command the write to buffer program confirm (29h) command is used to confirm a write to buffer program command and to program the n + 1 words/bytes loaded in the program buffer by this command. buffered program abort and reset command a buffered program abort and reset (f0h) command must be issued to reset the device to read mode when the buffer program operation is aborted. the buffer programming sequence can be aborted in the following ways: ? load a value that is greater than the page buffer size during the number of locations to program in the write to buffer program command. ? write to an address in a different block than the one specified during the write buf- fer load command. ? write an address/data pair to a different write buffer page than the one selected by the starting address during the program buffer data loading stage of the operation. ? write data other than the confirm command after the specified number of data load cycles. the abort condition is indicated by dq1 = 1, dq7 = dq7# (for the last address location loaded), dq6 = toggle, and dq5 = 0 (all of which are status register bits). a buffered program abort and reset command sequence must be written to reset the device for the next operation. note: the full three-cycle buffered program abort and reset command se- quence is required when using buffer programming features in unlock bypass mode. program suspend command the program suspend (b0h) command can be used to interrupt a program opera- tion so that data can be read from any block. when the program suspend command is issued during a program operation, the device suspends the operation within the pro- gram suspend latency time and updates the status register bits. after the program operation has been suspended, data can be read from any address. however, data is invalid when read from an address where a program operation has been suspended. 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 31 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
the program suspend command may also be issued during a program operation while an erase is suspended. in this case, data may be read from any address not in erase suspend or program suspend mode. to read from the extended memory block area (one-time programmable area), the enter/exit extended memory block command sequences must be issued. the system may also issue the auto select command sequence when the device is in program suspend mode. the system can read as many auto select codes as required. when the device exits auto select mode, the device reverts to program suspend mode and is ready for another valid operation. the program suspend operation is aborted by performing a device reset or power- down. in this case, data integrity cannot be ensured, and the words or bytes that were aborted should be reprogrammed. program resume command the program resume (30h) command must be issued to exit a program suspend mode and resume a program operation. the controller can use dq7 or dq6 status bits to determine the status of the program operation. after a program resume command is issued, subsequent program resume commands are ignored. another program suspend command can be issued after the device has resumed program- ming. enter and exit enhanced buffered program command the enhanced buffered program commands are available only in x16 mode. when the enter enhanced buffered program command is issued, the device accepts only these commands, which can be executed multiple times. monitor the tog- gle bit to ensure successful completion of the enter enhanced buffered pro- gram command. the exit enhanced buffered program command returns the device to read mode; two bus write operations are required to issue the command. enhanced buffered program command the enhanced buffered program command makes use of a 256-word write buf- fer to speed up programming. each write buffer has the same a[23:8] addresses. this command dramatically reduces system programming time compared to both the standard non-buffered program command and the write to buffer command. when issuing the enhanced buffered program command, the v pp /wp pin can be held high or raised to v pph . (see program/erase characteristics.) the following suc- cessive steps are required to issue the write to buffer program command: first, the enter enhanced buffered program command is issued. next, one bus write cycle sets up the enhanced buffered program command. the set-up code can be addressed to any location within the targeted block. then, a second bus write cycle loads the first address and the data to be programmed. there are a total of 256 address- and data-loading cycles. when the 256 words are loaded to the buffer, a third write cycle programs the content of the buffer. last, when the command com- pletes, the exit enhanced buffered program command is issued. address/data cycles must be loaded in an increasing address order, from a[7:0] = 00000000 to a[7:0] = 11111111 until all 256 words are loaded. invalid address combina- 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 32 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
tions or the incorrect sequence of bus write cycles will abort the write to buffer program command. the status register bits dq1, dq5, dq6, dq7 can be used to monitor the device status during a write to buffer program operation. an external 12v supply can be used to improve programming efficiency. when reprogramming data in a portion of memory already programmed (changing programmed data from 0 to 1) operation failure can be detected by a logical or be- tween the previous and the current value. 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 33 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 9: enhanced buffered program flowchart enhanced buffered program command set start read dq5 and dq6 at valid address dq6 = toggle dq5 =1 read dq6 twice at valid address dq6 = toggle fail read dq6 at valid address read status register (dq1, dq5, dq7) at last loaded address dq7 = data check status register (dq5, dq7) at last loaded address dq5 = 1 dq7 = data (3) enhanced buffered program confirm, block address fail or abort (4) 258th write cycle of the command enhanced buffered program end new program? exit enhanced buffered program command set yes yes yes yes yes yes yes no no no dq1 = 1 yes no no no no no x = x-1 write buffer data, start address (00), x=255 x = 0 no abort write to buffer write next data, (2) program address pair yes write to a different block address enhanced buffered program aborted (1) enhanced buffered program command, block address write next data, (2) program address pair first cycle of the enhanced buffered program command yes no 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 34 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
notes: 1. the enhanced buffered program abort and reset command must be issued to return the device to read mode. 2. when the block address is specified, all addresses in the selected block address space must be issued starting from 00h. furthermore, when loading the write buffer address with data, data program addresses must be consecutive. 3. dq7 must be checked because dq5 and dq7 may change simultaneously. 4. if this flowchart location is reached because dq5 = 1, then the enhanced write to buffer program command failed. if this flowchart location is reached because dq1 = 1, then the enhanced write to buffer program command aborted. in both cases, the appropriate reset command must be issued to return the device to read mode: a reset command if the operation failed; an enhanced write to buffer program abort and reset command if the operation aborted. enhanced buffered program abort and reset command an enhanced buffered program abort and reset command must be issued to reset the device to read mode when the enhanced buffered program opera- tion is aborted. the buffer programming sequence can be aborted in the following ways: ? write to an address in a different block than the one specified during the buffer load. ? write an address/data pair to a different write buffer page than the one selected by the starting address during the program buffer data loading stage of the operation. ? write data other than the confirm command after the 256 data load cycles. ? load a value that is greater than or less than the 256 buffer size. ? load address/data pairs in an incorrect sequence. the abort condition is indicated by dq1 = 1, dq6 = toggle, and dq5 = 0 (all of which are status register bits). 256mb: 3v embedded parallel nor flash program operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 35 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
erase operations chip erase command the chip erase (80/10h) command erases the entire chip. six bus write operations are required to issue the command and start the program/erase controller. protected blocks are not erased. if all blocks are protected, the chip erase operation appears to start, but will terminate within approximately100 s, leaving the data un- changed. no error is reported when protected blocks are not erased. during the chip erase operation, the device ignores all other commands, including erase suspend. it is not possible to abort the operation. all bus read operations dur- ing chip erase output the status register on the data i/os. (see the status register sec- tion for more details.) after the chip erase operation completes, the device returns to read mode, unless an error has occurred. if an error occurs, the device will continue to output the status regis- ter. a read/reset command must be issued to reset the error condition and return to read mode. the chip erase command sets all of the bits in unprotected blocks of the device to 1. all previous data is lost. the operation is aborted by performing a reset or by powering-down the device. in this case, data integrity cannot be ensured, and the entire chip should be erased again. unlock bypass chip erase command when the device is in unlock bypass mode, the unlock bypass chip erase (80/10h) command can be used to erase all memory blocks at one time. the command requires only two bus write operations instead of six using the standard chip erase com- mand. the final bus write operation starts the program/erase controller. the unlock bypass chip erase command behaves the same way as the chip erase command: the operation cannot be aborted, and a bus read operation to the memory outputs the status register. block erase command the block erase (80/30h) command erases a list of one or more blocks. it sets all of the bits in the unprotected selected blocks to 1. all previous data in the selected blocks is lost. six bus write operations are required to select the first block in the list. each addition- al block in the list can be selected by repeating the sixth bus write operation using the address of the additional block. after the command sequence is written, a block erase timeout occurs. during the timeout period, additional block addresses and block erase commands can be written. after the program/erase controller has started, it is not possible to select any more blocks. each additional block must therefore be selected within the timeout period of the last block. the timeout timer restarts when an addi- tional block is selected. after the sixth bus write operation, a bus read operation out- puts the status register. (see the we#-controlled program waveforms for details on how to identify if the program/erase controller has started the block erase operation.) 256mb: 3v embedded parallel nor flash erase operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 36 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
after the block erase operation completes, the device returns to read mode, unless an error has occurred. if an error occurs, bus read operations will continue to output the status register. a read/reset command must be issued to reset the error condi- tion and return to read mode. if any selected blocks are protected, they are ignored, and all the other selected blocks are erased. if all the selected blocks are protected, the block erase operation appears to start, but will terminate within approximately100 s, leaving the data unchanged. no error condition is given when protected blocks are not erased. during the block erase operation, the device ignores all commands except the erase suspend command and the read/reset command, which is accepted only during the timeout period. the operation is aborted by performing a reset or powering- down the device. in this case, data integrity cannot be ensured, and the aborted blocks should be erased again. unlock bypass block erase command when the device is in unlock bypass mode, the unlock bypass block erase (80/30h) command can be used to erase one or more memory blocks at a time. the command requires two bus write operations instead of six using the standard block erase command. the final bus write operation latches the address of the block and starts the program/erase controller. to erase multiple blocks (after the first two bus write operations have selected the first block in the list), each additional block in the list can be selected by repeating the sec- ond bus write operation using the address of the additional block. the unlock bypass block erase command behaves the same way as the block erase command: the operation cannot be aborted, and a bus read operation to the memory outputs the status register. (see the block erase command section for de- tails.) erase suspend command the erase suspend (b0h) command temporarily suspends a block erase opera- tion. one bus write operation is required to issue the command. the block address is "don't care." the program/erase controller suspends the erase operation within the erase suspend latency time of the erase suspend command being issued. however, when the erase suspend command is written during the block erase timeout, the device im- mediately terminates the timeout period and suspends the erase operation. after the program/erase controller has stopped, the device operates in read mode, and the erase is suspended. during an erase suspend operation, it is possible to read and execute program op- erations or write to buffer program operations in blocks that are not suspended. both read and program operations behave normally on these blocks. reading from blocks that are suspended will output the status register. if any attempt is made to pro- gram in a protected block or in the suspended block, the program command is ignor- ed, and the data remains unchanged. in this case, the status register is not read, and no error condition is given. 256mb: 3v embedded parallel nor flash erase operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 37 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
it is also possible to issue auto select and unlock bypass commands during an erase suspend operation. the read/reset command must be issued to return the device to read array mode before the resume command will be accepted. during an erase suspend operation, a bus read operation to the extended memory block will output the extended memory block data. after the device enters extended memory block mode, the exit extended memory block command must be issued before the erase operation can be resumed. an erase suspend command is ignored if it is written during a chip erase opera- tion. if the erase suspend operation is aborted by performing a device reset or power- down, data integrity cannot be ensured, and the suspended blocks should be erased again. erase resume command the erase resume (30h) command restarts the program/erase controller after an erase suspend operation. the device must be in read array mode before the resume command will be accepted. an erase can be suspended and resumed more than once. 256mb: 3v embedded parallel nor flash erase operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 38 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
block protection command definitions C address/data cycles table 12: block protection command definitions C address/data cycles, 8-bit and 16-bit notes 1 and 2 apply to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th n th a d a d a d a d a d lock register commands enter lock register command set (40h) x8 aaa aa 555 55 aaa 40 3 x16 555 aa 2aa 55 555 program lock register (a0h) x8 x a0 x data 5 x16 read lock register x8 x data 4, 5, 6 x16 password protection commands enter password protection command set (60h) x8 aaa aa 555 55 aaa 60 3 x16 555 aa 2aa 55 555 program password (a0h) x8 x a0 pwan pwdn 7 x16 read password x8 00 pwd0 01 pwd1 02 pwd2 03 pwd3 07 pwd7 4, 6, 8, 9 x16 00 pwd0 01 pwd1 02 pwd2 03 pwd3 unlock password (25h/ 03h) x8 00 25 00 03 00 pwd0 01 pwd1 00 29 8, 10 x16 nonvolatile protection commands enter nonvolatile protection command set (c0h) x8 aaa aa 555 55 aaa c0 3 x16 555 aa 2aa 55 555 program nonvolatile protection bit (a0h) x8 x a0 bad 00 x16 read nonvolatile protection bit status x8 bad read(0) 4, 6, 11 x16 clear all nonvolatile protection bits (80h/ 30h) x8 x 80 00 30 12 x16 nonvolatile protection bit lock bit commands enter nonvolatile protection bit lock bit command set (50h) x8 aaa aa 555 55 aaa 50 3 x16 555 aa 2aa 55 555 program nonvolatile protection bit lock bit (a0h) x8 x a0 x 00 11 x16 256mb: 3v embedded parallel nor flash block protection command definitions C address/data cycles pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 39 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 12: block protection command definitions C address/data cycles, 8-bit and 16-bit (continued) notes 1 and 2 apply to entire table command and code/subcode bus size address and data cycles notes 1st 2nd 3rd 4th n th a d a d a d a d a d read nonvolatile protection bit lock bit status x8 x read(0) 4, 6, 11 x16 volatile protection commands enter volatile protection command set (e0h) x8 aaa aa 555 55 aaa e0 3 x16 555 aa 2aa 55 555 program volatile protection bit (a0h) x8 x a0 bad 00 x16 read volatile protection bit status x8 bad read(0) 4, 6, 11 x16 clear volatile protection bit (a0h) x8 x a0 bad 01 x16 extended memory block commands enter extended memory block (88h) x8 aaa aa 555 55 aaa 88 3 x16 555 aa 2aa 55 555 exit extended memory block (90h/00h) x8 aaa aa 555 55 aaa 90 x 00 x16 555 aa 2aa 55 555 exit protection commands exit protection command set (90h/00h) x8 x 90 x 00 3 x16 notes: 1. key: a = address and d = data; x = "dont care"; bad = any address in the block; pwdn = password bytes 0 to 7; pwan = password address, n = 0 to 7; gray = not applicable. all values in the table are hexadecimal. 2. dq[15:8] are "dont care" during unlock and command cycles. a[max:16] are "dont care" during unlock and command cycles, unless an address is required. 3. the enter command sequence must be issued prior to any operation. it disables read and write operations from and to block 0. read and write operations from and to any other block are allowed. also, when an enter command set command is issued, an exit protection command set command must be issued to return the device to read mode. 4. read register/password commands have no command code; ce# and oe# are driven low, and data is read according to a specified address. 5. data = lock register content. 6. all address cycles shown for this command are read cycles. 7. only one portion of the password can be programmed or read by each program pass- word command. 8. each portion of the password can be entered or read in any order as long as the entire 64-bit password is entered or read. 256mb: 3v embedded parallel nor flash block protection command definitions C address/data cycles pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 40 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
9. for the x8 read password command, the n th (and final) address cycle equals the eighth address cycle. from the fifth to the eighth address cycle, the values for each ad- dress and data pair continue the pattern shown in the table as follows: for x8, address and data = 04 and pwd4; 05 and pwd5; 06 and pwd6; 07 and pwd7. 10. for the x8 unlock password command, the n th (and final) address cycle equals the eleventh address cycle. from the fifth to the tenth address cycle, the values for each ad- dress and data pair continue the pattern shown in the table as follows: address and data = 02 and pwd2; 03 and pwd3; 04 and pwd4; 05 and pwd5; 06 and pwd6; 07 and pwd7. for the x16 unlock password command, the n th (and final) address cycle equals the seventh address cycle. for the fifth and sixth address cycles, the values for the address and data pair continue the pattern shown in the table as follows: address and data = 02 and pwd2; 03 and pwd3. 11. both nonvolatile and volatile protection bit settings are as follows: protected state = 00; unprotected state= 01. 12. the clear all nonvolatile protection bits command programs all nonvolatile pro- tection bits before erasure. this prevents over-erasure of previously cleared nonvolatile protection bits. 256mb: 3v embedded parallel nor flash block protection command definitions C address/data cycles pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 41 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
protection operations blocks can be protected individually against accidental program, erase, or read op- erations on both 8-bit and 16-bit configurations. the block protection scheme is shown in the software protection scheme figure. memory block and extended memory block protection is configured through the lock register. lock register commands the enter lock register command set (40h) command enables execution of all read or program lock register commands. program lock register (a0h) configures the lock register, and read lock register reads/confirms programmed data. password protection commands the enter password protection command set (60h) command enables execu- tion of password protection commands. program password (a0h) programs the 64- bit password used in the password protection mode. to program the 64-bit password in 8-bit mode, the complete command sequence must be entered eight times at eight con- secutive addresses selected by a[1:0] plus dq15/a-1; in 16-bit mode, the command se- quence must be entered four times at four consecutive addresses selected by a[1:0]. by default, all password bits are set to 1. the password can be checked by issuing a read password command. read password verifies the password used in password protection mode. to verify the 64-bit password in 8-bit mode, the complete command sequence must be entered eight times at eight consecutive addresses selected by a[1:0] plus dq15/a-1. in 16-bit mode, the command sequence must be entered four times at four consecutive address- es selected by a[1:0]. if the password mode lock bit is programmed, and a user attempts to read the password, the device outputs ffh. unlock password (25/03h) clears the nonvolatile protection bit lock bit, allowing the nonvolatile protection bits to be modified. unlock password must be issued with the correct password and requires a 1 s delay between successive unlock pass- word commands. the delay helps prevent password intruders from trying all possible 64-bit combinations. if the delay does not occur, the latest command is ignored. after a valid 64-bit password is entered, approximately 1 s is required to unlock the device. nonvolatile protection commands the enter nonvolatile protection command set (c0h) command enables nonvolatile protection mode commands to be issued to the device. a block can be pro- tected from program or erase operations using a program nonvolatile pro- tection bit (a0h) command, along with the block address. this command sets the nonvolatile protection bit to 0 for a given block. the status of a nonvolatile protection bit for a given block or group of blocks can be read using a read nonvolatile modify protection bit command, along with the block address. the nonvolatile protection bits are erased simultaneously using a clear all nonvolatile protection bits (80/30h) command. no specific block address is required. if the nonvolatile protection bit lock bit is set to 0, the command fails. 256mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 42 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 10: program/erase nonvolatile protection bit algorithm no no yes yes dq6 = toggle enter nonvolatile protection command set start program nonvolatile protection bit addr = bad fail read byte twice addr = bad read byte twice addr = bad no no yes yes dq6 = toggle reset dq5 = 1 exit protection command set dq0 = 1 (erase) 0 (program) read byte twice addr = bad wait 500s pass 256mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 43 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
nonvolatile protection bit lock bit commands after the enter nonvolatile protection bit lock bit command set (50h) command has been issued, the commands that allow the nonvolatile protection bit lock bit to be set can be issued to the device. the program nonvolatile protection bit lock bit (a0h) command is used to set the nonvolatile protection bit lock bit to 0, thus locking the nonvolatile protection bits and preventing them from being modified. the read nonvolatile protection bit lock bit status command is used to read the status of the nonvolatile protection bit lock bit. volatile protection commands after the enter volatile protection command set (e0h) command has been issued, commands related to the volatile protection mode can be issued to the device. the program volatile protection bit (a0h) command individually sets a vola- tile protection bit to 0 for a given block. if the nonvolatile protection bit for the same block is set, the block is locked regardless of the value of the volatile protection bit. (see the block protection status table.) the status of a volatile protection bit for a given block can be read by issuing a read volatile protection bit status command along with the block address. the clear volatile protection bit (a0h) command individually clears (sets to 1) the volatile protection bit for a given block. if the nonvolatile protection bit for the same block is set, the block is locked regardless of the value of the volatile protection bit. (see the block protection status table.) extended memory block commands the device has one extra 128-word extended memory block that can be accessed only by the enter extended memory block (88h) command. the extended memory block is 128 words (x16) or 256 bytes (x8). it is used as a security block to provide a per- manent 128-bit security identification number or to store additional information. the device can be shipped with the extended memory block prelocked permanently by mi- cron, including the 128-bit security identification number. or, the device can be ship- ped with the extended memory block unlocked, enabling customers to permanently program and lock it. (see lock register, the auto select command, and the block protection table.) table 13: extended memory block address and data address data x8 x16 micron-prelocked customer-lockable 000000hC0000ffh 000000hC00007fh secure id number determined by customer after the enter extended memory block command has been issued, the device enters the extended memory block mode. all bus read or program operations are conducted on the extended memory block, and the extended memory block is ad- dressed using the addresses occupied by block 0 in the other operating modes. (see the memory map table.) 256mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 44 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
in extended memory block mode, erase, chip erase, erase suspend, and erase resume commands are not allowed. the extended memory block cannot be erased, and each bit of the extended memory block can only be programmed once. the extended memory block is protected from further modification by programming lock register bit 0. once invoked, this protection cannot be undone. the device remains in extended memory block mode until the exit extended mem- ory block (90/00h) command is issued, which returns the device to read mode, or until power is removed from the device. after a power-up sequence or hardware reset, the device will revert to reading memory blocks in the main array. exit protection command the exit protection command set (90/00h) command is used to exit the lock register, password protection, nonvolatile protection, volatile protection, and nonvola- tile protection bit lock bit command set modes and return the device to read mode. 256mb: 3v embedded parallel nor flash protection operations pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 45 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
device protection hardware protection the v pp /wp# function provides a hardware method of protecting the highest or lowest block. when v pp /wp# is low, program and erase operations on either of these blocks is ignored to provide protection. when v pp /wp# is high, the device reverts to the previous protection status for the highest or lowest block. program and erase operations can modify the data in this block unless the block is protected using block protection. when v pp /wp# protect is raised to v pph , the device automatically enters the unlock by- pass mode, and command execution time is faster. this must never be done from any mode except read mode; otherwise, the device might be left in an indeterminate state. a 0.1 f capacitor should be connected between v pp /wp# and the v ss ground pin to de- couple the current surges from the power supply. the pcb track widths must be suffi- cient to carry the currents required during unlock bypass program. when v pp /wp# returns to high or low, normal operation resumes. when operations execute in unlock bypass mode, the device draws i pp from the pin to supply the pro- gramming circuits. transitions from high to v pph and from v pph to low must be slow- er than t vhvpp. note: micron highly recommends driving v pp /wp# high or low. if a system needs to float v pp /wp#, without a pull-up/pull-down resistor and no capacitor, then an internal pull-up resistor is enabled. table 14: v pp /wp# functions v pp /wp# settings function v il highest (29wxxxgh) or lowest (29wxxxgl) block is protected. v ih highest or lowest block is unprotected unless software protection is activated. v pph unlock bypass mode supplies current necessary to speed up program execution time. software protection software protection includes volatile, nonvolatile, and password protection as well as password access. the device is shipped with all blocks unprotected. on first use, the de- vice defaults to the nonvolatile protection mode but can be activated in either the non- volatile protection or password protection mode. the desired protection mode is activated by setting either the nonvolatile protection mode lock bit or the password protection mode lock bit of the lock register. (see the lock register section.) both bits are one-time-programmable and nonvolatile; there- fore, after the protection mode has been activated, it cannot be changed, and the device is set permanently to operate in the selected protection mode. it is recommended that the desired software protection mode be activated when first programming the device. for the lowest and highest blocks, a higher level of block protection can be achieved by locking the blocks using nonvolatile protection mode and holding v pp /wp# low. 256mb: 3v embedded parallel nor flash device protection pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 46 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
blocks with volatile protection and nonvolatile protection can coexist within the memo- ry array. if the user attempts to program or erase a protected block, the device ignores the command and returns to read mode. the block protection status can be read by performing a read electronic signature or by issuing an auto select command. (see the block protection table.) refer to the block protection status table and the software protection scheme figure for details on the block protection scheme. refer to the protection operations section for a description of the command sets. volatile protection mode volatile protection enables the software application to protect blocks against inadver- tent change and can be disabled when changes are needed. volatile protection bits are unique for each block and can be individually modified. volatile protection bits control the protection scheme only for unprotected blocks whose nonvolatile protection bits are cleared to 1. issuing a program volatile protection bit or clear volatile protection bit command sets to 0 or clears to 1 the volatile protection bits and pla- ces the associated blocks in the protected (0) or unprotected (1) state, respectively. the volatile protection bit can be set or cleared as often as needed. when the device is first shipped, or after a power-up or hardware reset, the volatile pro- tection bits default to 1 (unprotected). nonvolatile protection mode a nonvolatile protection bit is assigned to each block. each of these bits can be set for protection individually by issuing a program nonvolatile protection bit com- mand. also, each device has one global volatile bit called the nonvolatile protection bit lock bit; it can be set to protect all nonvolatile protection bits at once. this global bit must be set to 0 only after all nonvolatile protection bits are configured to the desired settings. when set to 0, the nonvolatile protection bit lock bit prevents changes to the state of the nonvolatile protection bits. when cleared to 1, the nonvolatile protection bits can be set and cleared using the program nonvolatile protection bit and clear all nonvolatile protection bits commands, respectively. no software command unlocks the nonvolatile protection bit lock bit unless the device is in password protection mode; in nonvolatile protection mode, the nonvolatile protec- tion bit lock bit can be cleared only by taking the device through a hardware reset or power-up. nonvolatile protection bits cannot be cleared individually; they must be cleared all at once using a clear all nonvolatile protection bits command. they will re- main set through a hardware reset or a power-down/power-up sequence. if one of the nonvolatile protection bits needs to be cleared (unprotected), additional steps are required. first, the nonvolatile protection bit lock bit must be cleared to 1, us- ing either a power-cycle or hardware reset. then, the nonvolatile protection bits can be changed to reflect the desired settings. finally, the nonvolatile protection bit lock bit must be set to 0 to lock the nonvolatile protection bits. the device now will operate nor- mally. to achieve the best protection, the program nonvolatile protection lock bit command should be executed early in the boot code, and the boot code should be pro- tected by holding v pp /wp# low. 256mb: 3v embedded parallel nor flash device protection pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 47 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
nonvolatile protection bits and volatile protection bits have the same function when v pp /wp# is high or when v pp /wp# is at the voltage for program acceleration (v pph ). password protection mode password protection mode provides a higher level of security than the nonvolatile pro- tection mode by requiring a 64-bit password to unlock the nonvolatile protection bit lock bit. in addition to this password requirement, the nonvolatile protection bit lock bit is set to 0 after power-up and reset to maintain the device in password protection mode. executing the unlock password command by entering the correct password clears the nonvolatile protection bit lock bit, enabling the block nonvolatile protection bits to be modified. if the password provided is incorrect, the nonvolatile protection bit lock bit remains locked, and the state of the nonvolatile protection bits cannot be modified. to place the device in password protection mode, the following two steps are required: first, before activating the password protection mode, a 64-bit password must be set and the setting verified. password verification is allowed only before the password pro- tection mode is activated. next, password protection mode is activated by program- ming the password protection mode lock bit to 0. this operation is irreversible. after the bit is programmed, it cannot be erased, the device remains permanently in password protection mode, and the 64-bit password can be neither retrieved nor reprogrammed. in addition, all commands to the address where the password is stored are disabled. note: there is no means to verify the password after password protection mode is ena- bled. if the password is lost after enabling the password protection mode, there is no way to clear the nonvolatile protection bit lock bit. figure 11: software protection scheme 1 = unprotected (default) 0 = protected 1 = unprotected 0 = protected (default setting depends on the product order option) volatile protection bit nonvolatile protection bit 1 = unlocked (default, after power-up or hardware reset) 0 = locked nonvolatile protection bit lock bit (volatile) nonvolatile protection mode password protection mode volatile protection nonvolatile protection array block notes: 1. volatile protection bits are programmed and cleared individually. nonvolatile protection bits are programmed individually and cleared collectively. 2. once programmed to 0, the nonvolatile protection bit lock bit can be reset to 1 only by taking the device through a power-up or hardware reset. 256mb: 3v embedded parallel nor flash device protection pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 48 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
common flash interface the common flash interface (cfi) is a jedec-approved, standardized data structure that can be read from the flash memory device. it allows a system's software to query the device to determine various electrical and timing parameters, density information, and functions supported by the memory. the system can interface easily with the de- vice, enabling the software to upgrade itself when necessary. when the read cfi command is issued, the device enters cfi query mode, and the da- ta structure is read from memory. the following tables show the addresses (a-1, a[7:0]) used to retrieve the data. the query data is always presented on the lowest order data outputs (dq[7:0]), and the other data outputs (dq[15:8]) are set to 0. table 15: query structure overview note 1 applies to entire table address subsection name description x16 x8 10h 20h cfi query identification string command set id and algorithm data offset 1bh 36h system interface information device timing and voltage information 27h 4eh device geometry definition flash device layout 40h 80h primary algorithm-specific extended query table additional information specific to the primary al- gorithm (optional) 61h c2h security code area 64-bit unique device number note: 1. query data are always presented on the lowest order data outputs (dq[7:0]). dq[15:8] are set to 0. table 16: cfi query identification string note 1 applies to entire table address data description value x16 x8 10h 20h 0051h query unique ascii string "qry" "q" 11h 22h 0052h "r" 12h 24h 0059h "y" 13h 14h 26h 28h 0002h 0000h primary algorithm command set and control interface id code 16-bit id code defining a specific algorithm C 15h 16h 2ah 2ch 0040h 0000h address for primary algorithm extended query table (see the primary algo- rithm-specific extended query table.) p = 40h 17h 18h 2eh 30h 0000h 0000h alternate vendor command set and control interface id code second ven- dor-specified algorithm supported C 19h 1ah 32h 34h 0000h 0000h address for alternate algorithm extended query table C note: 1. query data are always presented on the lowest-order data outputs (dq[7:0]). dq[15:8] are set to 0. 256mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 49 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 17: cfi query system interface information note 1 applies to entire table address data description value x16 x8 1bh 36h 0027h v cc logic supply minimum program/erase voltage bits[7:4] bcd value in volts bits[3:0] bcd value in 100mv 2.7v 1ch 38h 0036h v cc logic supply maximum program/erase voltage bits[7:4] bcd value in volts bits[3:0] bcd value in 100mv 3.6v 1dh 3ah 00b5h v pph (programming) supply minimum program/erase voltage bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 11.5v 1eh 3ch 00c5h v pph (programming) supply maximum program/erase voltage bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 12.5v 1fh 3eh 0004h typical timeout for single byte/word program = 2 n s 16s 20h 40h 0004h typical timeout for maximum size buffer program = 2 n s 16s 21h 42h 0009h typical timeout per individual block erase = 2 n ms 0.5s 22h 44h 0011h typical timeout for full chip erase = 2 n ms 80s 23h 46h 0004h maximum timeout for byte/word program = 2 n times typical 200s 24h 48h 0004h maximum timeout for buffer program = 2 n times typical 200s 25h 4ah 0003h maximum timeout per individual block erase = 2 n times typical 2.3s 26h 4ch 0004h maximum timeout for chip erase = 2 n times typical 800s note: 1. the values in this table are valid for both packages. table 18: device geometry definition address data description value x16 x8 27h 4eh 0019h device size = 2 n in number of bytes 32mb 28h 29h 50h 52h 0002h 0000h flash device interface code description x8, x16 asynchronous 2ah 2bh 54h 56h 0006h 0000h maximum number of bytes in multibyte program or page = 2 n 64b 2ch 58h 0001h number of erase block regions. it specifies the number of regions containing contiguous erase blocks of the same size. 1 2dh 2eh 5ah 5ch 00ffh 0000h erase block region 1 information number of identical-size erase blocks = 00ffh + 1 256 block 2fh 30h 5eh 60h 0000h 0002h erase block region 1 information block size in region 1 = 0200h 256 bytes 128kb 256mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 50 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 18: device geometry definition (continued) address data description value x16 x8 31h 32h 33h 34h 62h 64h 66h 68h 0000h 0000h 0000h 0000h erase block region 2 information 0 35h 36h 37h 38h 6ah 6ch 6eh 70h 0000h 0000h 0000h 0000h erase block region 3 information 0 39h 3ah 3bh 3ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h erase block region 4 information 0 table 19: primary algorithm-specific extended query table note 1 applies to entire table address data description value x16 x8 40h 80h 0050h primary algorithm extended query table unique ascii string pri "p" 41h 82h 0052h "r" 42h 84h 0049h "i" 43h 86h 0031h major version number, ascii "1" 44h 88h 0033h minor version number, ascii "3" 45h 8ah 0010h address-sensitive unlock (bits[1:0]): 00 = required 01 = not required silicon revision number (bits[7:2]) yes 65nm 46h 8ch 0002h erase suspend: 00 = not supported 01 = read only 02 = read and write 2 47h 8eh 0001h block protection: 00 = not supported x = number of blocks per group 1 48h 90h 0000h temporary block unprotect: 00 = not supported 01 = supported 00 49h 92h 0008h block protect/unprotect: 06 = m29w256gh/m29w256gl 06 4ah 94h 0000h simultaneous operations: not supported C 256mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 51 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 19: primary algorithm-specific extended query table (continued) note 1 applies to entire table address data description value x16 x8 4bh 96h 0000h burst mode: 00 = not supported 01 = supported 00 4ch 98h 0002h page mode: 00 = not supported 02 = 8-word page 02 4dh 9ah 00b5h v pph supply minimum program/erase voltage: bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 11.5v 4eh 9ch 00c5h v pph supply maximum program/erase voltage: bits[7:4] hex value in volts bits[3:0] bcd value in 100mv 12.5v 4fh 9eh 00xxh top/bottom boot block flag: xx = 04h: m29w256gl, first block protected by v pp /wp# xx = 05h: m29w256gh, last block protected by v pp /wp# uniform + v pp /wp# protect- ing highest or lowest block 50h a0h 0001h program suspend: 00 = not supported 01 = supported 01 note: 1. the values in this table are valid for both packages. table 20: security code area address data description x16 x8 61h c3h, c2h xxxx 64-bit unique device number 62h c5h, c4h xxxx 63h c7h, c6h xxxx 64h c9h, c8h xxxx 256mb: 3v embedded parallel nor flash common flash interface pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 52 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
power-up and reset characteristics table 21: power-up wait timing specifications note 1 applies to entire table parameter symbol min unit notes legacy jedec v cc high to ce# low t vch t vchel 55 s 2, 3 v ccq high to ce# low C t vcqhel 55 s 2, 3 v cc high to we# low C t vchwl 500 s v ccq high to we# low C t vcqhwl 500 ns notes: 1. specifications apply to 60, 70, and 80ns devices unless otherwise noted. the 60ns device is available upon customer request. 2. v cc and v ccq ramps must be synchronized during power-up. 3. if rst# is not stable for t vcs or t vios, the device will not allow any read or write oper- ations, and a hardware reset is required. figure 12: power-up timing v cc t vcqhel ce# v ccq t vcqhwl we# t vchel t vchwl 256mb: 3v embedded parallel nor flash power-up and reset characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 53 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 22: reset ac specifications note 1 applies to entire table condition/parameter symbol min max unit notes legacy jedec rst# low to read mode during program or erase t ready t plrh C 55 s 2 rst# pulse width t rp t plph 20 C s rst# high to ce# low, oe# low t rh t phel, t phgl, t phwl 55 C ns 2 rst# low to standby mode during read mode t rpd C 20 C s rst# low to standby mode during program or erase 55 C s ry/by# high to ce# low, oe# low t rb t rhel, t rhgl, t rhwl 0 C ns 2 notes: 1. specifications apply to 60, 70, and 80ns devices unless otherwise noted. the 60ns device is available upon customer request. 2. sampled only; not 100% tested. figure 13: reset ac timing C no program/erase operation in progress t rh ry/by# ce#, oe#, we# rst# t rp 256mb: 3v embedded parallel nor flash power-up and reset characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 54 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 14: reset ac timing during program/erase operation t rb ry/by# ce#, oe#, we# rst# t rp t rh t ready 256mb: 3v embedded parallel nor flash power-up and reset characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 55 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
absolute ratings and operating conditions stresses greater than those listed may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other condi- tions outside those indicated in the operational sections of this specification is not im- plied. exposure to absolute maximum rating conditions for extended periods may ad- versely affect reliability. table 23: absolute maximum/minimum ratings parameter symbol min max unit notes temperature under bias t bias C50 125 c storage temperature t stg C65 150 c i/o voltage v io C0.6 v cc + 0.6 v 1, 2 supply voltage v cc C0.6 4 v i/o supply voltage v ccq C0.6 4 v identification voltage v id C0.6 13.5 v program voltage v pph C0.6 13.5 v 3 notes: 1. during signal transitions, minimum voltage may undershoot to ?2v for periods less than 20ns. 2. during signal transitions, maximum voltage may overshoot to v cc + 2v for periods less than 20ns. 3. v pph must not remain at 12v for more than 80 hours cumulative. table 24: operating conditions note 1 applies to entire table parameter symbol min max unit notes supply voltage v cc 2.7 3.6 v input/output supply voltage (v ccq v cc ) v ccq 1.65 3.6 v 2 ambient operating temperature (range 1) t a 0 70 c ambient operating temperature (range 6) t a C40 125 c load capacitance c l 30 pf input rise and fall times C C 10 ns input pulse voltages C 0 to v ccq v input and output timing reference voltages C v ccq /2 v notes: 1. specifications apply to 60, 70, and 80ns devices unless otherwise noted. the 60ns device is available upon customer request. 2. for the 80ns device, i/o supply voltage (v ccq v cc ) = 1.65v (min) and 3.6v (max). for the 60ns and 70ns devices, i/o supply voltage (v ccq v cc ) = 2.7v (min) and 3.6v (max). 256mb: 3v embedded parallel nor flash absolute ratings and operating conditions pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 56 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 15: ac measurement load circuit c l v ccq 25k device under test 0.1f v cc 0.1f v pp 25k note: 1. c l includes jig capacitance. figure 16: ac measurement i/o waveform v ccq 0v v ccq /2 table 25: i/o capacitance 1 parameter symbol test condition min max unit input capacitance c in v in = 0v C 6 pf output capacitance c out v out = 0v C 12 pf note: 1. sampled only; not 100% tested. 256mb: 3v embedded parallel nor flash absolute ratings and operating conditions pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 57 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
dc characteristics table 26: dc current characteristics parameter symbol conditions min typ max unit notes input leakage current i li 0v v in v cc C C 1 a 1 output leakage current i lo 0v v out v cc C C 1 a v cc read current random read i cc1 ce# = v il , oe# = v ih , f = 6 mhz C C 10 ma page read ce# = v il , oe# = v ih , f = 10 mhz C C 1 ma v cc standby current grade 6 i cc2 ce# = v ccq 0.2v, rst# = v ccq 0.2v C C 100 a 2 grade 3 C C 200 a 2 v cc program/erase current i cc3 program/ erase controller active v pp /wp# = v il or v ih C C 20 ma 3 v pp /wp# = v pph C C 15 ma v pp current read i pp1 v pp /wp# v cc C 1 5 a standby C 1 5 a reset i pp2 rst# = v ss 0.2v C 1 5 a program operation ongoing i pp3 v pp /wp# = 12v 5% C 1 10 ma v pp /wp# = v cc C 1 5 a erase operation ongoing i pp4 v pp /wp# = 12v 5% C 3 10 ma v pp /wp# = v cc C 1 5 a notes: 1. the maximum input leakage current is 5a on the v pp /wp# pin. 2. when the bus is inactive for t avqv +30ns or more, the memory enters automatic stand- by. 3. sampled only; not 100% tested. 256mb: 3v embedded parallel nor flash dc characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 58 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 27: dc voltage characteristics parameter symbol conditions min typ max unit notes input low voltage v il v cc 2.7v C0.5 C 0.3v ccq v input high voltage v ih v cc 2.7v 0.7v ccq C v ccq + 0.4 v output low voltage v ol i ol = 100a, v cc = v cc,min , v ccq = v ccq,min C C 0.15v ccq v output high voltage v oh i oh = 100a, v cc = v cc,min , v ccq = v ccq,min 0.85v ccq C C v identification voltage v id C 11.5 C 12.5 v voltage for v pp /wp# program acceleration v pph C 11.5 C 12.5 v program/erase lockout supply voltage v lko C 1.8 C 2.5 v 1 note: 1. sampled only; not 100% tested. 256mb: 3v embedded parallel nor flash dc characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 59 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
read ac characteristics table 28: read ac characteristics parameter symbol condition 60ns v ccq = v cc 70ns v ccq = v cc 80ns v ccq = 1.65v to v cc unit notes min max min max min max legacy jedec address valid to next ad- dress valid t rc t avav ce# = v il , oe# = v il 60 C 70 C 80 C ns address valid to output valid t acc t avqv ce# = v il , oe# = v il C 60 C 70 C 80 ns address valid to output valid (page) t page t avqv1 ce# = v il , oe# = v il C 25 C 25 C 30 ns ce# low to output transition t lz t elqx oe# = v il 0 C 0 C 0 C ns 2 ce# low to output valid t e t elqv oe# = v il C 60 C 70 C 80 ns oe# low to output transition t olz t glqx ce# = v il 0 C 0 C 0 C ns 2 oe# low to output valid t oe t glqv ce# = v il C 25 C 25 C 30 ns ce# high to output high-z t hz t ehqz oe# = v il C 25 C 25 C 30 ns 2 oe# high to output high-z t df t ghqz ce# = v il C 25 C 25 C 30 ns 2 ce#, oe#, or address transition to output transition t oh t ehqx, t ghqx, t axqx C 0 C 0 C 0 C ns t ehqv ce# to byte# low t elfl t elbl C C 5 C 5 C 5 ns ce# to byte# high t elfh t elbh C C 5 C 5 C 5 ns t elqz byte# low to output high-z t flqz t blqz C C 25 C 25 C 30 ns byte# high to output valid t fhqv t bhqv C C 30 C 30 C 30 ns notes: 1. the 60ns device is available upon customer request. 2. sampled only; not 100% tested. 256mb: 3v embedded parallel nor flash read ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 60 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 17: random read ac timing (8-bit mode) valid valid t acc t rc t oh t ce t elfl t lz t oh t hz t olz t oh t oe t df a[max:0]/a-1 ce# oe# dq[7:0] byte# note: 1. byte# = v il figure 18: random read ac timing (16-bit mode) valid valid t acc t rc t oh t e t elfh t lz t oh t hz t olz t oh t oe t df a[max:0] ce# oe# dq[14:0] dq15a-1 byte# 256mb: 3v embedded parallel nor flash read ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 61 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 19: page read ac timing (16-bit mode) valid valid valid valid valid valid valid valid t acc t e t page t oh t hz t oh t oe t df a[max:3] a[2:0] ce# oe# dq[15:0] dq15a-1 valid valid valid valid valid valid valid note: 1. page size is 8 words (16 bytes) and is addressed by address inputs a[2:0] in x16 bus mode and a[2:0] plus dq15/a?1 in x8 bus mode. 256mb: 3v embedded parallel nor flash read ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 62 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
write ac characteristics table 29: we#-controlled write ac characteristics parameter symbol 60ns 2 v ccq = v cc 70ns v ccq = v cc 80ns v ccq = 1.65v to v cc unit notes legacy jedec min max min max min max address valid to next address valid t wc t avav 65 C 75 C 85 C ns ce# low to we# low t cs t elwl 0 C 0 C 0 C ns we# low to we# high t wp t wlwh 35 C 35 C 35 C ns input valid to we# high t ds t dvwh 45 C 45 C 45 C ns 2 we# high to input transition t dh t whdx 0 C 0 C 0 C ns we# high to ce# high t ch t wheh 0 C 0 C 0 C ns we# high to we# low t wph t whwl 30 C 30 C 30 C ns address valid to we# low t as t avwl 0 C 0 C 0 C ns we# low to address transi- tion t ah t wlax 45 C 45 C 45 C ns oe# high to we# low C t ghwl 0 C 0 C 0 C ns we# high to oe# low t oeh t whgl 0 C 0 C 0 C ns program/erase valid to ry/by# low t busy t whrl C 30 C 30 C 30 ns 3 v cc high to ce# low t vcs t vchel 50 C 50 C 50 C s notes: 1. the 60ns device is available upon customer request. 2. the user's write timing must comply with this specification. any violation of this write timing specification may result in permanent damage to the nor flash device. 3. sampled only; not 100% tested. 256mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 63 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 20: we#-controlled program ac timing (8-bit mode) aaah pa pa 3rd cycle 4th cycle read cycle data polling t wc t wc t as t wp t ds t whwh1 t df t wph t ah t ce t cs t ghwl t oe t dh t oh t ch a[max:0]/a-1 ce# oe# we# dq[7:0] a0h pd dq7# d out d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit and by a read operation that outputs the data (d out ) programmed by the previous program command. 2. pa is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7. (see data polling bit [dq7].) 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 256mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 64 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 21: we#-controlled program ac timing (16-bit mode) 555h pa pa 3rd cycle 4th cycle read cycle data polling t wc t wc t as t wp t ds t df t whwh1 t wph t ah t e t cs t ghwl t oe t dh t oh t ch a[max:0] ce# oe# we# dq[14:0]/a-1 aoh pd dq7# d out d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit and by a read operation that outputs the data (d out ) programmed by the previous program command. 2. pa is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7. (see data polling bit [dq7].) 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 256mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 65 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
table 30: ce#-controlled write ac characteristics parameter symbol 60ns 2 v ccq = v cc 70ns v ccq = v cc 80ns v ccq = 1.65v to v cc unit notes legacy jedec min max min max min max address valid to next address valid t wc t avav 65 C 75 C 85 C ns we# low to ce# low t ws t wlel 0 C 0 C 0 C ns ce# low to ce# high t cp t eleh 35 C 35 C 35 C ns input valid to ce# high t ds t dveh 45 C 45 C 45 C ns 2 ce# high to input transition t dh t ehdx 0 C 0 C 0 C ns ce# high to we# high t wh t ehwh 0 C 0 C 0 C ns ce# high to ce# low t cph t ehel 30 C 30 C 30 C ns address valid to ce# low t as t avel 0 C 0 C 0 C ns ce# low to address transition t ah t elax 45 C 45 C 45 C ns oe# high to ce# low C t ghel 0 C 0 C 0 C ns notes: 1. the 60ns device is available upon customer request. 2. the user's write timing must comply with this specification. any violation of this write timing specification may result in permanent damage to the nor flash device. 256mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 66 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 22: ce#-controlled program ac timing (8-bit mode) aaah pa pa 3rd cycle 4th cycle data polling t wc t as t cp t ds t whwh1 t cph t ah t ws t ghel t dh t wh a[max:0]/a-1 we# oe# ce# dq[7:0] a0h pd dq7# d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit. 2. pa is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7. (see data polling bit [dq7].) 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 256mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 67 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 23: ce#-controlled program ac timing (16-bit mode) 555h pa pa 3rd cycle 4th cycle data polling t wc t as t cp t ds t whwh1 t cph t ah t ws t ghel t dh t wh a[max:0] we# oe# ce# dq[14:0]/a-1 aoh pd dq7# d out notes: 1. only the third and fourth cycles of the program command are represented. the pro- gram command is followed by checking of the status register data polling bit. 2. pa is the address of the memory location to be programmed. pd is the data to be pro- grammed. 3. dq7 is the complement of the data bit being programmed to dq7. (see data polling bit [dq7].) 4. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 256mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 68 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 24: chip/block erase ac timing (8-bit mode) aaah t wc t as t wp t ds t wph t ah t cs t ghwl t dh t ch a[max:0]/ aC1 ce# oe# we# dq[7:0] aah 555h aaah aaah bah 1 555h aaah 55h 55h aah 80h 10h/ 30h notes: 1. for a chip erase command, the address is aaah, and the data is 10h; for a block erase command, the address is bad, and the data is 30h. 2. bad is the block address. 3. see the following tables for timing details: read ac characteristics, we#-controlled write ac characteristics, and ce#-controlled write ac characteristics. 256mb: 3v embedded parallel nor flash write ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 69 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
accelerated program, data polling/toggle ac characteristics table 31: accelerated program and data polling/data toggle ac characteristics note 1 and 2 apply to entire table parameter symbol min max unit legacy jedec v pp /wp# rising or falling time C t vhvpp 250 C ns address setup time to oe# low during toggle bit polling t aso t axgl 10 C ns address hold time from oe# during toggle bit polling t aht t ghax, t ehax 10 C ns ce# high during toggle bit polling t eph t ehel2 10 C ns output hold time during data and toggle bit polling t oeh t whgl2, t ghgl2 20 C ns program/erase valid to ry/by# low t busy t whrl C 30 ns notes: 1. specifications apply to 60, 70, and 80ns devices unless otherwise noted. the 60ns device is available upon customer request. 2. sampled only; not 100% tested. figure 25: accelerated program ac timing t vhvpp t vhvpp v pph v il or v ih v pp /wp# 256mb: 3v embedded parallel nor flash accelerated program, data polling/toggle ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 70 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 26: data polling ac timing dq7# data dq7# valid dq7 data output flag data output flag valid dq[6:0] data t hz/ t df t ce t oe t oph t ch t busy t oeh ce# oe# we# dq[6:0] dq7 ry/by# notes: 1. dq7 returns a valid data bit when the program or erase command has completed. 2. see the following tables for timing details: read ac characteristics, accelerated pro- gram and data polling/data toggle ac characteristics. figure 27: toggle/alternative toggle bit polling ac timing (8-bit mode) toggle toggle toggle data stop toggling output valid t busy t oph t eph t oeh ce# we# oe# dq6/dq2 ry/by# t oph t aht t aso t aht t dh t aso a[max:0]/ aC1 t oe t ce notes: 1. dq6 stops toggling when the program or erase command has completed. dq2 stops toggling when the chip erase or block erase command has completed. 2. see the following tables for timing details: read ac characteristics, accelerated pro- gram and data polling/data toggle ac characteristics. 256mb: 3v embedded parallel nor flash accelerated program, data polling/toggle ac characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 71 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
program/erase characteristics table 32: program/erase characteristics notes 1 and 2 apply to entire table parameter min typ max unit notes chip erase C 145 400 s 3, 4 chip erase v pp /wp# = v pph C 125 400 s 4 block erase (128kb) C 0.5 2 s 4, 5 erase suspend latency time C 25 45 s block erase timeout 50 C C s erase to suspend C 1 C ms 6 byte program single-byte program C 16 200 s 4 write to buffer program (64 bytes at a time) v pp /wp# = v pph C 50 200 s 4 v pp /wp# = v ih C 70 200 s 4 word program single-word program C 16 200 s 4 write to buffer program (32 words at a time) v pp /wp# = v pph C 50 200 s 4 v pp /wp# = v ih C 70 200 s 4 chip program (byte by byte) C 540 800 s 4 chip program (word by word) C 270 400 s 4 chip program (write to buffer program) C 25 200 s 4, 7 chip program (write to buffer program with v pp /wp# = v pph ) C 13 50 s 4, 7 chip program (enhanced buffered program) C 15 60 s 7 chip program (enhanced buffered program with v pp /wp# = v pph ) C 10 40 s 7 program suspend latency time C 5 15 s program/erase cycles (per block) 100,000 C C cycles data retention 20 C C years notes: 1. typical values are measured at room temperature and nominal voltages and are not for cycled devices. 2. typical and maximum values are sampled, but not 100% tested. 3. time needed to program the whole array at 0 is included. 4. maximum value measured at worst case conditions for both temperature and v cc after 100,000 program/erase cycles. 5. block erase polling cycle time. (see the data polling ac waveforms figure.) 6. erase to suspend is the typical time between an initial block erase or erase resume command and a subsequent erase suspend command. violating the specification re- peatedly during any particular block erase may cause erase failures. 7. intrinsic program timing means without the time required to execute the bus cycles to load the program commands. 256mb: 3v embedded parallel nor flash program/erase characteristics pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 72 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
package dimensions figure 28: 56-pin tsop C 14mm x 20mm see detail a 0.50 typ 14.00 0.10 1.20 max 18.40 0.10 20.00 0.20 1.00 0.05 0.10 0.05 0.22 0.05 detail a 0.50 0.10 0.10 0.10 min/ 0.21 max pin #1 3 / 5 o o notes: 1. all dimensions are in millimeters. 2. for the lead width value of 0.22 0.05, there is also a legacy value of 0.15 0.05. 256mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 73 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 29: 64-ball tbga C 10mm x 13mm ball "a1" 0.10 max 0.50 typ 1.00 typ 0.80 typ 1.20 max 1.50 typ 3.00 typ 0.50 typ 7.00 typ 7.00 typ 10.00 0.10 13.00 0.10 0.35 min/ 0.50 max 0.30 -0.10 +0.05 note: 1. all dimensions are in millimeters. 256mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 74 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
figure 30: 64-ball fortified bga C 11mm x 13mm seating plane 0.80 typ 0.10 13.00 0.10 0.60 0.05 1.00 typ 3.00 typ a b c d e f g h 7.00 typ 1.40 max ball a1 id 1.00 typ 2.00 typ 0.48 0.05 11.00 0.10 7.00 typ 64x 8 7 6 5 4 3 2 1 note: 1. all dimensions are in millimeters. 256mb: 3v embedded parallel nor flash package dimensions pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 75 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.
revision history rev. c C 7/13 ? minor text edits ? added erase to suspend specifications to program/erase characteristics rev. b C 5/13 ? synchronized tbga (za) package dimensions in the order information table with di- mensions in the package diagram rev. a C 5/12 ? initial micron brand release 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 www.micron.com/productsupport customer comment line: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 256mb: 3v embedded parallel nor flash revision history pdf: 09005aef84bd3b68 m29w_256mb.pdf - rev. c 7/13 en 76 micron technology, inc. reserves the right to change products or specifications without notice. ? 2013 micron technology, inc. all rights reserved.

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